The researchers used a cellulose material for the substrate of the chip, which is the part that supports the active semiconductor layer. Taken from cellulose, a naturally abundant substance used to make paper, cellulose nanofibril (CNF) is a flexible, transparent and sturdy material with suitable electrical properties.
Source: Computer chips made of wood promise greener electronics
In a conventional chip, the support substrate is made of the same material as the active layer, but in the CNF chip, only the active layer is semiconductor material
Kahng says chipmakers may face a more immediate struggle with wiring in just a few years as they attempt to push chip density down past the 10-nm generation. Each copper wire requires a sheath containing barrier material to prevent the metal from leaching into surrounding material, as well as insulation to prevent it from interacting with neighboring wires. To perform effectively, this sheath must be fairly thick. This thickness limits how closely wires can be pushed together and forces the copper wires to shrink instead, dramatically driving up the resistance and delays and drastically lowering performance. Although researchers are exploring alternative materials, it’s unclear, Kahng says, whether they will be ready in time to keep up with Moore’s Law’s steady pace.
via The Status of Moore’s Law: It’s Complicated – IEEE Spectrum.
To help you keep things straight, we’ve assembled this handy guide that will walk you through the basics of how an SoC is put together. It will also serve as a guide to most of the current (and future, where applicable) chips available from the big players making SoCs today: Apple, Qualcomm, Samsung, Nvidia, Texas Instruments, Intel, and AMD.
via The PC inside your phone: A guide to the system-on-a-chip | Ars Technica.
SoC=System on a Chip
A research group based at the Korea Institute of Science and Technology (KIST) in Seoul, South Korea, has developed a circuit that may get around these problems. The device, described in a paper published on Nature’s website on 30 January, uses magnetism to control the flow of electrons across a minuscule bridge of the semiconducting material indium antimonide (S. Joo et al. Nature http://dx.doi.org/10.1038/nature11817; 2013). It is “a new and interesting twist on how to implement a logic gate”, says Gian Salis, a physicist at IBM’s Zurich Research Laboratory in Switzerland.
via Magnetic logic makes for mutable chips : Nature News & Comment.
This seems like a revolutionary discovery if it can be manufactured relatively easily. And then there’s this:
But Johnson notes that magnetism is already catching on in circuit design: some advanced devices are beginning to use a magnetic version of random access memory, a type of memory that has historically been built only with conventional transistors. “I think a shift is already under way,” he says.
The low-power chip makes it possible to interact with mobile devices and a host of other consumer electronics using hand gesture recognition, which today is usually accomplished with camera-based sensors. A key limitation is that it only recognizes motions, such as a hand flick or circular movement, within a six-inch range.
via A New Chip Brings Electrical-Field-Based 3-D Gesture Recognition to Smartphones | MIT Technology Review.
The controller comes with the ability to recognize 10 predefined gestures, including wake-up on approach, position tracking, and various hand flicks, but it can also be programmed to respond to custom movements. Similar to the programming of voice recognition software, Microchip Technology built the gesture library using algorithms that learned from how different people make the same movements. These gestures can then be translated to functions on a device, such as on/off, open application, point, click, zoom, or scroll.
EZchip and Netronome both sell network processors — chips specifically designed for networking equipment — and both say they’re expanding their scope to cover Layers 2 through 7, thanks to their new chip designs. That means they can target switching, routing, security, deep packet inspection — pretty much all the intelligence in a network element.
via Light Reading – Optical Networking – Chips Race to Absorb the Line Card – Telecom News Analysis.
But just four years later, Bryant says, the landscape has completely changed. Today, she explains, eight server makers account for 75 percent of Intel’s server chip revenues, and at least one of those eight doesn’t even sell servers. It only makes servers for itself. “Google is something like number five on that list,” Bryant told us on Monday evening, during a dinner with reporters in downtown San Francisco.
That’s right, Google is likely the world’s fifth largest server maker.
via Intel Confirms Decline of Server Giants HP, Dell, and IBM | Wired Enterprise | Wired.com.
Terabit switch chips and switch chipsets that scale up to 400 Tbit/s are making merchant switch chips very attractive for high-performance network systems against in-house ASIC and FPGA-based designs. The latest switch devices not only deliver on performance, but integrate additional system functions such as Ethernet MACs and programmable classification engines to support software-defined networking (SDN).
via Light Reading – Market Leaders Drive Investment in Switching – Telecom.
High-performance switch devices have become both more complicated and simpler. The devices integrate additional functionality with significant on-chip memory and packet processing functions. On the other hand, the interfaces for most protocols are moving to 10 Gbit/s for the current generation and 25 Gbit/s for the next generation.
The 450mm wafers would help solve the problem of rising costs in making advanced chips, allowing TSMC to provide affordable 10 nanometer chips with FinFET transistors for customers, J.K. Wang (王建光), vice president of TSMC’s operation in charge of 300mm factories, told a media briefing arranged by semiconductor industry association SEMI.
via TSMC plans 450mm wafers by 2018 – Taipei Times.
Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer.
PORTLAND, Ore.—The first automated software-to-chip dream came out of the closet Monday April 23, when Algotochip Corp. Sunnyvale, Calif. claimed to be able to produce a system-on-chip SoC design from a C-code specification in just eight to 16 weeks.
via Startup claims ‘Holy Grail’ of SoC design.