Tag Archives: cpu

US-CERT Vulnerability Note VU#649219 – SYSRET 64-bit operating system privilege escalation vulnerability on Intel CPU hardware

Posted on by

A ring3 attacker may be able to specifically craft a stack frame to be executed by ring0 (kernel) after a general protection exception (#GP). The fault will be handled before the stack switch, which means the exception handler will be run at ring0 with an attacker’s chosen RSP causing a privilege escalation.

via US-CERT Vulnerability Note VU#649219 – SYSRET 64-bit operating system privilege escalation vulnerability on Intel CPU hardware.

Details from Red Hat

RHSA-2012:0720-1 & RHSA-2012:0721-1: It was found that the Xen hypervisor implementation as shipped with Red Hat Enterprise Linux 5 did not properly restrict the syscall return addresses in the sysret return path to canonical addresses. An unprivileged user in a 64-bit para-virtualized guest, that is running on a 64-bit host that has an Intel CPU, could use this flaw to crash the host or, potentially, escalate their privileges, allowing them to execute arbitrary code at the hypervisor level. (CVE-2012-0217, Important)

AMD Licenses ARM Technology: AMD Leans on ARM for Security

Posted on by

Last year after that particular AFDS, there was much speculation that AMD and ARM would get a whole lot closer. Today we have confirmed that in two ways. The first is that AMD and ARM are founding members of the HSA Foundation. This endeavor is a rather ambitious project that looks to make it much easier for programmers to access the full computer power of a CPU/GPU combo, or as AMD likes to call them, the APU. The second confirmation is one that has been theorized for quite some time, but few people have actually hit upon the actual implementation. This second confirmation is that AMD is licensing ARM cores and actually integrating them into their x86 based APUs.

via AMD Licenses ARM Technology: AMD Leans on ARM for Security | PC Perspective.

ARM expects 20-nanometer processors by late next year

Posted on by

ARM doesn’t manufacture the chips itself. It licenses its designs to companies such as Qualcomm, Texas Instruments and Nvidia, who in turn outsource manufacture of the chips to foundry companies like Taiwan’s TSMC.

via ARM expects 20-nanometer processors by late next year – processors, Components, Arm Holdings, computex – CIO.

This year’s Computex should be a big event for ARM. Microsoft has developed the first version of its Windows PC OS that runs on ARM-based processors, called Windows RT, and vendors are expected to show the first ARM-based tablets running the new software.

AMD launches Trinity processors: the Ivy Bridge alternative

Posted on by

Trinity is being aimed at ultrathin notebooks (not to be confused with Intel Ultrabooks), smaller form factor desktops and All-in-Ones, though traditional mainstream laptops and desktops will also see Trinity APUs. AMD will be launching five APUs today. The A10-4600M, A8-4500M, and A6-4400M are aimed at larger, mainstream notebooks, while the A10-4655M and A6-4455M are destined for sleeker ultrathin models.

AMD’s Trinity APUs will mark the debut of the company’s Piledriver microarchitecture, the successor to the ill-received Bulldozer. Trinity is still based on a 32nm process — Intel, by contrast, recently moved to 22nm with Ivy Bridge. Trinity’s die size is actually a bit larger than Llano’s: 246 square millimeters, compared to the first generation APU’s 228 square millimeters. Trinity also features a higher transistor count at 1.3 billion, but dials the TDP for its notebook variants down to 17W for dual-core CPUs, and 35W for quad-core CPUs, the same as Ivy Bridge — Llano APUs required 35W and 45W for dual- and quad-core, respectively. Desktop Trinity remain at the same 65 to 100W of its Llano predecessors. AMD claims that the dual-core Trinity APU will perform at the same level as the dual-core Llano APU, effectively doubling the performance per watt with the new generation. AMD also claims that Trinity notebooks can expect as 12 hours of battery life (when idle) on their energy efficient Piledriver cores.

via AMD launches Trinity processors: the Ivy Bridge alternative | The Verge.

China plans national, unified CPU architecture

Posted on by

According to reports from various industry sources, the Chinese government has begun the process of picking a national computer chip instruction set architecture (ISA). This ISA would have to be used for any projects backed with government money — which, in a communist country such as China, is a fairly long list of public and private enterprises and institutions, including China Mobile, the largest wireless carrier in the world. The primary reason for this move is to lessen China’s reliance on western intellectual property.

via China plans national, unified CPU architecture | ExtremeTech.

The other option, of course, is developing a brand new ISA — a daunting task, considering you have to create an entire software (compiler, developer, apps) and hardware (CPU, chipset, motherboard) ecosystem from scratch. But, there are benefits to building your own CPU architecture. China, for example, could design an ISA (or microarchicture) with silicon-level monitoring and censorship — and, of course, a ubiquitous, always-open backdoor that can be used by Chinese intelligence agencies. The Great Firewall of China is fairly easy to circumvent — but what if China built a DNS and IP address blacklist into the hardware itself?

Intel Core i7-3770K Review: A Small Step Up For Ivy Bridge : Ivy Bridge: Was It Worth The Wait?

Posted on by

Intel built Sandy Bridge-based chips in three different configurations: one quad-core and two dual-core designs. The most complex implementation included 995 million transistors in a 216 mm² piece of silicon. In comparison, the biggest Ivy Bridge die incorporates 1.4 billion transistors on a 160 mm² die.

via Intel Core i7-3770K Review: A Small Step Up For Ivy Bridge : Ivy Bridge: Was It Worth The Wait?.

All told, Ivy Bridge is yet another highly integrated processor design from Intel. Its pieces were constructed by independent teams throughout the world—engineers in Israel are responsible for the IA cores, a team in Folsom, CA built the graphics engine, and a second team in Folsom implemented the interconnects, cache, and system agent. Of course, a process development group up in Oregon made sure it’d all come together on the new 22 nm node.

Xeon E5-2600 Review

Posted on by

http://www.anandtech.com/show/5553/the-xeon-e52600-dual-sandybridge-for-servers

Intel’s Sandy Bridge architecture was introduced to desktop users more than a year ago. Server parts however have been much slower to arrive, as it has taken Intel that long to transpose this new engine into a Xeon processor. Although the core architecture is the same, the system architecture is significantly different from the LGA-1155 CPUs, making this CPU quite a challenge, even for Intel.

 

The Opteron 6276: a closer look

Posted on by

First let’s look at the pricing. The Opteron 6276 is priced similar to an E5649, which is clocked 5% lower than the X5650 we tested. If you calculate the price of a Dell R710 with the Xeon E5649 and compare it with a Dell R715 with the Opteron 6276 with similar specs, you end up more or less the same acquisition cost. However, the E5649 is an 80W TDP and should thus consume a bit less power. That is why we argued that the Opteron 6276 should at least offer a price/performance bonus and perform like an X5650. The X5650 is roughly $220 more expensive, so you end up with the dual socket Xeon system costing about $440 more. On a fully speced server, that is about a 10% price difference.

via AnandTech – The Opteron 6276: a closer look.

ARM Discloses Technical Details Of The Next Version Of The…

Posted on by

“The current growth trajectory of data centers, driven by the viral explosion of social media and cloud computing, will continue to accelerate. The ability to handle this data increase with energy-efficient solutions is vital,” said Vinay Ravuri, vice president and general manager of AppliedMicro’s Processor Business Unit. “The ARM 64-bit architecture provides the right balance of performance, efficiency and cost to scale to meet these growing demands and we are very excited to be a leading partner in implementing solutions based on the ARMv8 architecture.”

via ARM Discloses Technical Details Of The Next Version Of The… – ARM.

CPU Startup Combines CPU+DRAM

Posted on by

There are three limiting factors, or walls, that limit the scaling of modern microprocessors. First, there’s the memory wall, defined as the gap between the CPU and DRAM clock speed. Second, there’s the ILP (Instruction Level Parallelism) wall, which refers to the difficulty of decoding enough instructions per clock cycle to keep a core completely busy. Finally, there’s the power wall–the faster a CPU is and the more cores it has, the more power it consumes.

via CPU Startup Combines CPU+DRAM – HotHardware.

When your CPU has fewer transistors than an architecture that debuted in 1986, it’s a good chance that you left a few things out–like an FPU, branch prediction, pipelining, or any form of speculative execution. Venray may have created a chip with power consumption an order of magnitude lower than anything ARM builds and more memory bandwidth than Intel’s highest-end Xeons, but it’s an ultra-specialized, ultra-lightweight core that trades 25 years of flexibility and performance for scads of memory bandwidth.