CPU Startup Combines CPU+DRAM

There are three limiting factors, or walls, that limit the scaling of modern microprocessors. First, there’s the memory wall, defined as the gap between the CPU and DRAM clock speed. Second, there’s the ILP (Instruction Level Parallelism) wall, which refers to the difficulty of decoding enough instructions per clock cycle to keep a core completely busy. Finally, there’s the power wall–the faster a CPU is and the more cores it has, the more power it consumes.

via CPU Startup Combines CPU+DRAM – HotHardware.

When your CPU has fewer transistors than an architecture that debuted in 1986, it’s a good chance that you left a few things out–like an FPU, branch prediction, pipelining, or any form of speculative execution. Venray may have created a chip with power consumption an order of magnitude lower than anything ARM builds and more memory bandwidth than Intel’s highest-end Xeons, but it’s an ultra-specialized, ultra-lightweight core that trades 25 years of flexibility and performance for scads of memory bandwidth.